Field programmable device, such as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD), can be configured to implement various logical functions. The logical functions can include, for example, an arithmetic operation (e.g., addition, subtraction, multiplication and division of input data), a control processing (e.g., generating a sequence of states and outputs at pre-determined times based on input data), etc. Logic functions for arithmetic operations and control processing can be implemented using a combination of combinational logic blocks and sequential logic blocks. However, logic blocks for arithmetic operations are typically dominated by combinational logic blocks, while logic blocks for control processing are typically dominated by sequential logic blocks.
A field programmable device includes an array of programmable logic blocks, which may include a set of look-up tables, combinational logic gates, flip flops, and routing matrices, as well as components including embedded memories, input/output buffers, phased locked loops (PLL), delay locked loops (DLL), clock buffers, etc. These logic blocks and components can be configured, using a hardware description language (HDL) such as VHDL, Verilog, etc., to implement the aforementioned logic functions. The HDL can be configured to describe the behaviors of certain logic blocks (e.g., an arithmetic logic unit for arithmetic operation, a finite state machine to generate a sequence of states and outputs, etc.). A software compiler can compile a program file that includes HDL associated with the logic blocks, and generate a set of low level programming instructions. The low level programming instructions can then configure the logic blocks and components (e.g., look-up tables, flip flops, and routing matrices, etc.) of the field programmable device to implement the logic functions.
Different field programmable devices may have different technical specifications, such as a number of components (e.g., look-up tables that implement the combinational logic gates, flip flops, routing matrices, etc.) available for configuration. The number of components can be expressed in terms of an aggregate gate count that represents a total number of equivalent NAND2 logic gates for all the available logic blocks (including combinational and sequential logic blocks). Under conventional technologies, a field programmable device is selected to implement a logic function, if an aggregate gate count associated with the logic function (e.g., an aggregate gate count associated with the combinational and sequential logic blocks for implementing the logic function) is below the available aggregate gate count of the field programmable device. The field programmable device is then configured using the HDL to implement the logic function.
The inventors here have recognized several technical problems with the conventional method of selecting and configuring the field programmable device. First, without distinguishing the gate counts for sequential logics and combinational logics for a logic function, the selected field programmable device may be ill-suited to implement that logic function. As discussed above, logic blocks for arithmetic operations are typically dominated by combinational logic blocks, while logic blocks for control processing are typically dominated by sequential logic blocks. A field programmable device with lots of combinational logic gates but relatively few flip flops available for configuration may not be suitable to implement a logic function for control processing, even if the aggregate gate count for that field programmable device exceeds the aggregate count associated with the logic function for control processing. Second, by selecting a field programmable device to implement a logic function based only on whether the aggregate gate count associated with the logic function is less than the available aggregate gate count of the field programmable device, the selected field programmable device can also become underutilized, if a majority of its devices (e.g., combinational logic gates, sequential logic blocks, etc.) are not needed to implement that logic function, which can lead to inefficient usage of field programmable device resources.